1. Field of the Invention
The present invention relates to a method and an apparatus of controlling a memory device, which generate an address signal supplied to a memory device based upon an address signal supplied from an outside.
2. Description of the Related Art
Software which operates on a microcomputer typically uses a ROM (Read Only Memory) and a RAM (Random Access Memory) as a resource in the microcomputer. The ROM is provided for storing a computer program and the RAM is provided for holding data generated in the program. In an EVA chip (evaluation chip), it is general to provide a device to physically operate as the RAM to an address space provided for the ROM and an address space provided for the RAM in view of easiness of program debug.
FIG. 6 is a block diagram showing an example of the configuration of the EVA chip and illustrates a relation of a RAM, a ROM, and a central processing unit (CPU). In FIG. 6, the RAM 62, the ROM 64, and a peripheral device 66 performing, for example, an interruption control or a DAM transfer control are connected to the CPU 60 through a bus 68, and further a debugger 70 is connected directly to the CPU 60. The debugger 70 is provided based upon JTAG (Joint Test Action Group) standard most of the time and the CPU 60 is directly controlled by use of ICE (In-circuit Emulator) debugger, to provide access to the bus 68. Further, a device which physically operates as the RAM is provided in each of the RAM 62 and the ROM 64.
FIG. 7 is a view of a detailed description of portions of the RAM 62 and the ROM 64 out of the configuration of the EVA chip shown in FIG. 6. In FIG. 7, an address decoder 80 receives and decodes an address signal 84 to be output from the CPU 60 to the bus 68, to generate an access signal 86 to indicate access to the ROM 64 and an access signal 88 to indicate access to the RAM 62. An address generation circuit 82 generates an address signal 90 supplied to the RAM 62 and the ROM 64 by receiving the address signal 84.
The RAM 62 receives the access signal 88 as an access enable, and writes in or reads out the data according to the address signal 90 supplied from the address generation circuit 82, and the ROM 64 receives the access signal 86 as an access enable, and writes in or reads out the data according to the address signal 90 supplied from the address generation circuit 82. Both the RAM 62 and the ROM 64 are devices that physically operate as the RAM as described before and the RAM 62 is used as RAM and the ROM 64 is used as ROM.
FIGS. 8 to 10 illustrate the excerpts of a ROM space and a RAM space with regard to an address space controlled by the CPU 60 in FIG. 6. In addition, the Address (ROM) and the Address (RAM) show a head address of the ROM space and a head address of the RAM space, respectively. In FIG. 8, the RAM device 0 (corresponding to the RAM 62) and the RAM device 1 (corresponding to the ROM 64) are located in a part of the RAM space from the Address (RAM). In FIG. 9 the RAM device 0 and the RAM device 1 are located in a part of the ROM space from the Address (ROM). In FIG. 10 the RAM device 0 and the RAM device 1 are located in parts of the RAM space and the ROM space from the Address (RAM) and the Address (ROM), respectively.
It is typical to sequentially access the RAM in ascending order, but there is a case where access to the RAM is sequentially made in descending order (for example, refer to Japanese Patent Laid-Open Publication No. H11-340958).
However, there is a case where a memory capacity of each physical RAM provided to the ROM space and the RAM space controlled by the CPU is desired to be changed freely depending on an object in use of a computer system. For example, a capacity ratio between the physical RAMs provided to the ROM space and the RAM space in the EVA chip controlled by the CPU is required to change flexibly so that the EVA chip is provided to developments of various software operated in the microcomputer. However, since it is not easy to change the physical RAM assembled inside an apparatus, the conventional configuration shown in FIG. 7 has the problem that it is difficult to change the memory capacity of the physical RAMs 62 and 64 provided to the ROM space and the RAM space, respectively.
A demand on changing the memory capacity can be met by mounting many physical RAMs each having a small memory capacity, but an increase of the number of physical RAMs to be mounted causes an increase of the mounting area or costs.